1. Field of Invention
The invention relates to a stress block structure of an electronic packaging, and more particularly to a structure for reducing stress for vias and a fabricating method thereof.
2. Related Art
In recent years, as the demands of electronic products in speed and volume have increased dramatically, the amount of the input/output (I/O) pins and the power of the chips are increasing accordingly.
Taking memory as an example, the volume of early memory was 16M or 64M. Now, memory has been developed to the Double Data Rate II Synchronous Dynamic Random Access Memory (DDRII SDRAM) with a volume of 512M. Difficulties in the process and the reliability of products have increasingly emerged; therefore, in order to achieve a single die with high volume or a stacked packaging with multiple die, the requirements of high volume and high speed are reached by the use of different package structures. Therefore, the signal contacts (I/O) at the chip terminal enter the area array I/O pins through less peripheral I/O pins. Thus, during redistribution, a required wire line needs to be plated on the chip pad in the thickness direction (i.e. the lines of different layers are connected through the vias) before redistribution is carried out. The wire (i.e. the via) in the thickness direction can be designed being plated completely or with blind vias. However, during the process, lateral stress will be generated owning to the temperature applied according to the process requirements, or the temperature cycling experiment carried out for the reliability test after the package is completed, or even the thermal effect resulting from the operation of the device or element, therefore the wire in the thickness direction is bound to endure the lateral thermal stress resulting from the change in temperature in the above cases regardless of the design thereof. Herein, the main reason for the thermal stress includes structure design, material selection, and the like, wherein, the effect of the material parameters, for example the Young's Modulus (E) and the Coefficient of Thermal Expansion (CTE), of the material itself on the thermal stress is most significant. Since there are generally various kinds of materials in different kinds of electronic devices or elements, the mismatched thermal stresses in the interface areas of different materials will be caused by the difference in the temperature distribution and the CTE of different materials. Thus, the telecommunicating contact is destroyed, for example the breaking of the wire in the thickness direction, thereby causing problems with product reliability. However, the physical characteristics subject to the material cannot be changed and the materials compatible with the process which can be selected for use are limited. Therefore, how to extend the service life of the electronic device or element by the use of a preferred structure design has gradually become one of the important research subjects regarding the electronic device or element.
Conventionally, in an electronic device or element, an insulating material with a low E will be used as a dielectric layer, so as to serve as a stress-buffering device. However, generally this kind of insulating material is a polymer material; therefore, although the material is characterized by a low E, it has a relatively large CTE. Considering the temperature cycling of the reliability, the wire in the thickness direction tends to endure large stress and dramatic deformation due to the large amount thermal expansion of the insulating material. At present, a common conventional method of solving this problem is to increase the thickness of the wall of the wire in the thickness direction or to fill the blind vias by plating the metal material so as to solve the problem of poor reliability. However, when the insulating material with a low E serves as a stress-buffering device, the stress buffering effect will be increased as the thickness of the insulating material is increased, whereas the ratio of depth to width of the wire in the thickness direction will be excessively large. Therefore, the problem resulting from the innate material cannot be effectively alleviated even if the structure which is designed with enlarged wall thickness or blind vias filled with metal materials is employed.
As shown in U.S. Pat. No. 6,586,822 and U.S. Pat. No. 6,586,836, which disclose a structure of embedding a chip in an organic substrate, wherein a flex component interposer is provided in both patents to serve as a stress absorbing layer, thereby overcoming the problems of stress and strain to be confronted with.